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AM79212/Am79C202
Advanced Subscriber Line Interface Circuit (ASLICTM) Device Advanced Subscriber Line Audio-Processing Circuit (ASLACTM) Device DISTINCTIVE CHARACTERISTICS
Single channel architecture Performs Battery-Feed, Ring-trip, Signaling, Coding, Hybrid, and Test (BORSCHT) functions Single hardware design meets multiple country requirements through software programming GCI Interface -- Control and PCM on one bus -- Data rate up to 4.096 MHz
Low idle power per line On-hook transmission Exceeds LSSGR and CCITT central office requirements Off-hook and ground-key detectors with programmable thresholds Programmable line feed characteristics independent of battery voltage Built-in voice path test modes Analog and digital hybrid balance capability Adaptive hybrid balance capability Linear power feed with power management and thermal shutdown features Abrupt and smooth polarity reversal Power cross detection in ringing and nonringing states Only Battery and +5 V supplies needed
Monitor of two-wire interface voltage and current for subscriber line diagnostics

Performs all of the functions of a CODEC-Filter
Software programmable -- -- -- -- -- -- -- -- -- DC loop feed characteristics and current limit Loop supervision detection thresholds Off-hook detect debounce interval Two-wire AC impedance Transhybrid balance Transmit and receive gains Equalization Digital I/O pins A-law/-law selection

Compatible with inexpensive protection networks. Accommodates low-tolerance fuse resistors while maintaining longitudinal balance to Bellcore specifications. Power/Service Denial state Small physical size Integrated ring-trip function Four relay drivers with built-in energy absorption zener diodes Synchronized ring relay operation: zero volts AC on, zero current off Software-enabled normal or automatic Ring-Trip state On-chip 12/16 kHz metering generation with onand off-meter pulse shaping Supports loop-start and ground-start signaling. 0C to 70C commercial operation guaranteed by production testing -40C to +85C temperature range operation available
Publication# 080165 Rev: C Amendment: /0 Issue Date: October 1999
TABLE OF CONTENTS
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Linecard Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ASLIC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ASLAC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Connection Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ASLIC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ASLAC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ASLIC/ASLAC Devices Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Absolute Maximum Electrical and Thermal Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ASLIC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ASLAC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Performance Characteristics (See Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ASLIC Device Relay Driver Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Switching CharacteristicS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Switching Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Input and Output Waveforms for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Data Clock Timing - DCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 GCI Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 ASLIC/ASLAC Devices Linecard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Physical Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
LIST OF FIGURES
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Transmit and Receive Path Attenuation vs. Frequency . . . . . . . . . . . . . . . . . . . 23 Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 A-law Gain Linearity with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . . . 25 -law Gain Linearity with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . . . 25 Total Distortion with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 A/A Overload Compression. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 ASLIC/ASLAC Typical Linecard Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
LIST OF TABLES
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ASLIC Device DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ASLIC Device Relay Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ASLIC Device Transmission Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ASLAC Device DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ASLAC Device Transmission and Signaling Specifications . . . . . . . . . . . . . . . . 19 Microprocessor Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Data Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 User-Programmable Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 ASLIC/ASLAC Devices Linecard Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2
AM79212/Am79C202 Data Sheet
The AM79212/Am79C202 Advanced Subscriber Line Interface chip set implements a universal telephone line interface function. This enables the design of a single, low-cost, high-performance, fully-software-programmable line interface card for multiple country applications world wide. All AC, DC, and Signaling parameters are fully programmable via the General Control Inter-
face (GCI). Additionally, the ASLIC device and ASLAC device have integrated self test and line test capabilities to resolve faults to the line or line circuit. The integrated test capability is crucial for remote applications where dedicated test hardware is not cost effective. Use of the accompanying Technical Reference, document PID 21324A is recommended.
LINECARD BLOCK DIAGRAM
Loop Voltage Sense Resistors
Transmit Receive
RFA A(Tip) Ring and Test Relays AD SA ASLIC Device SB BD DC Feed Control Metering Loop Voltage Monitor Loop Current Monitor B(Ring) RFB Relay Driver Outputs ASLIC Operating State Ring-Feed Resistor Relay Driver Inputs ASLAC Device GCI Backplane
Ringer Supply Ringing-Current Sense Resistors
ASLIC/ASLAC Products
3
ORDERING INFORMATION ASLIC Device
Legerity standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Must order Am79C202 with the device below.
AM79212 J C TEMPERATURE RANGE C = Commercial (0C to 70C)*
PACKAGE TYPE J = 32-pin Plastic Leaded Chip Carrier (PL 032)
DEVICE NUMBER/DESCRIPTION AM79212 Advanced Subscriber Line Interface Circuit
Valid Combinations AM79212 JC
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Legerity sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Note: * Functionality of the device from 0C to +70C is guaranteed by production testing. Performance from -40C to +85C is guaranteed by characterization and periodic sampling of production units.
4
AM79212/Am79C202 Data Sheet
ASLAC Device
Legerity standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Must order AM79212 with the part below.
Am79C202 J C TEMPERATURE RANGE C = Commercial (0C to 70C)*
PACKAGE TYPE J = 32-pin Plastic Leaded Chip Carrier (PL032)
DEVICE NUMBER/DESCRIPTION Am79C202 Advanced Subscriber Line Interface Circuit
Valid Combinations Am79C202 JC
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Legerity sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Note: * Functionality of the device from 0C to +70C is guaranteed by production testing. Performance from -40C to +85C is guaranteed by characterization and periodic sampling of production units.
ASLIC/ASLAC Products
5
CONNECTION DIAGRAMS Top View
32-Pin PLCC RY1OUT BGND
VCC
BD
AD
SB
4 RY2OUT RY3OUT RINGOUT TMG VBAT C5 C4 C3 C2 5 6 7 8 9 10 11 12 13
3
2
1
32 31
30 29 28 27 RSVD HPB HPA RSVD BAL1 BAL2 VREF VTX IDC
ASLIC Device AM79212
SA 26 25 24 23 22 21 20 RSN
14 15 C1 VDC
16 17 18 IDIF VLBIAS ISUM
19 GND
Note: RSVD = Reserved. Do not connect to this pin.
19780A-004
32-Pin PLCC DGND
4 DCL FS RST DD DU VCCD S1 S0 S2 5 6 7 8 9 10 11 12 13
3
2
1
32 31
30 29 28 27 IAB IREF VLBIAS VCCA IDIF ISUM IRTA IRTB IDC
ASLAC Device Am79C202
IBAT 26 25 24 23 22 21 20 VINM
I/O2
I/O1
O1
C2 AGND
14 15 I1 VM
16 17 18 19 VOUT VREF VIN
C1
19780A-003
6
AM79212/Am79C202 Data Sheet
PIN DESCRIPTIONS ASLIC Device
Pin Names AD, BD BAL1, BAL2 BGND C2-C1 C5-C3 Type Output Input Gnd Input Input Description A and B Line Drivers. These pins provide the currents to the A and B leads of the subscriber loop. Pre-balance. These pins receive voltages that are added to the VTX output signal. They can be used to cancel out the metering echo in the transmit path. Battery Ground. This pin connects to the ground return for Central Office or talk battery. ASLIC Device Control. These ternary logic input pins control the operating state of the ASLIC device. Test Relay Control. These are control inputs for the test relay drivers in the ASLIC device. A logic Low turns on the relay driver and activates the relay. C3 controls RY1OUT, C4 controls RY2OUT, and C5 controls RY3OUT. Analog and digital ground return for VCC. High-Pass Filter Capacitor Connections. These pins connect to CHP, the external highpass filter capacitor that isolates the DC control loop from the voice transmission path. DC Loop Control Current. The DC loop current control line from the ASLAC device is connected to this pin. An internal resistance is provided between the IDC pin and RSN. An external noise filter capacitor should be connected between this pin and VREF. A - B Leg Current. The current at this pin is proportional to the difference of the currents flowing out of the AD pin and into the BD pin of the ASLIC device. A + B Leg Current. The current at this pin is proportional to the absolute value of the sum of the currents flowing out of the AD pin and into the BD pin of the ASLIC device. Relay Drivers. These are open collector, high-current relay driver outputs with emitters internally connected to BGND. To absorb the inductive pulse from the relay coils, an internal Zener diode is connected between the collector of each driver and BGND. Receive Summing Node. The metallic current (both AC and DC) between AD and BD is equal to the ASLIC device current gain, K1, times the current into this pin. Networks that program receive gain and two-wire impedance connect to this node. This input is nominally at VREF potential. Reserved. This is used during Legerity testing. In the application, this pin must be floating. A and B Lead Voltage Sense. These pins sense the voltages on the line side of the fuse resistors at the A and B leads. External sense resistors, RSA and RSB, are required to protect these pins from lightning or power cross conditions. Thermal Management. A resistor connected from this pin to VBAT reduces the on-chip power dissipation by absorbing excess power from the ASLIC device for short loop conditions. Battery Voltage. This pin supplies battery voltage to the line drivers.
GND HPA, HPB IDC
Gnd Capacitor Input
IDIF ISUM RINGOUT, RY1OUT, RY2OUT, RY3OUT RSN
Output Output Output
Input
RSVD SA, SB
Input Input
TMG
Resistor
VBAT VCC VDC
Power Power Output
Power Supply. This pin is the positive supply for low-voltage analog and digital circuits in the ASLIC device.
DC Loop Voltage. The voltage on this output is referenced to VREF and is proportional to the negative absolute value of the DC subscriber loop voltage between A and B. This voltage is a fraction () of the voltage between HPA and HPB. This pin connects to the IAB pin on the ASLAC device through the external resistor RAB. A voltage that is significantly more positive than VREF on the VDC pin indicates that the ASLIC device is in thermal shutdown. Longitudinal Offset Voltage. The input to this pin is the offset reference voltage for the ASLIC device longitudinal control loop.
VLBIAS
Input
ASLIC/ASLAC Products
7
Pin Names VREF
Type Input
Description Analog Reference. This voltage is provided by the ASLAC device and is used by the ASLIC device for internal reference purposes. All analog input and output signals interfacing to the ASLAC device are referenced to this pin. Nominally set to 2.1 V. Four-Wire Transmit Signal. The voltage between this pin and VREF is a scaled version of the AC component of the voltage sensed between the SA and SB pins. One end of the two-wire input impedance programming network connects to VTX. The voltage at VTX swings positive and negative about VREF.
VTX
Output
ASLAC Device
Pin Names AGND C2-C1 Type Gnd Output Description Analog (Quiet) Ground. VREF is referenced to this ground. ASLIC Device Control. These ternary logic output pins are dedicated to controlling the operating state of the ASLIC device. The levels of these outputs are logic High, logic Low, and High impedance. GCI Clock. This input controls the clocking of the GCI data and is also used as the master clock for the CODEC and DSP. 2.048 MHz or 4.096 MHz clock frequencies can be used. In either case, the GCI bit rate is always 2.048 MHz. Downstream GCI Data. Downstream data is received serially on the DD port every 125 s at the DCL rate. Digital Ground. This is the digital ground return. Upstream GCI Data. Upstream data is sent serially on the DU pin every 125 s at the DCL rate. DU is high impedance between bursts. This pin is an open drain output. Frame Sync. The Frame Sync signal is an 8 kHz pulse that identifies the beginning of a GCI frame. The ASLAC device references the timing of back-plane data transfer to this input. The back-plane data bit rate must be synchronized to DCL. Control Port. This input port is TTL compatible and can be used to monitor an external TTL compatible device. The logic state of this pin appears in the I1 bit (bit 2) of the upstream C/I channel. Loop Voltage Sense. The IAB pin is a current summing node referenced to VREF. An external resistor (RAB) is connected between this pin and the VDC pin of the ASLIC device. In normal operation, current flows out of this pin. When the ASLIC device is in thermal shutdown, current will be forced into this pin. Battery Voltage Sense. The IBAT pin is a current summing node referenced to AGND and receives a current that is proportional to the system battery voltage. A sense resistor/capacitor network is connected between the VBAT pin of the ASLIC device and the IBAT pin. DC Loop Control Current. The IDC output supplies a current to the ASLIC device for proportional control of the DC loop current flowing through the subscriber loop. Longitudinal Sense. IDIF is a current input pin and is fed by the IDIF pin of the ASLIC device. The current in this pin is used by the ASLAC device for supervisory and diagnostic functions. The IDIF pin has an internal input resistance so an external longitudinal noisefilter capacitor can be connected. Control Ports. These control lines are TTL compatible and each can be programmed as an input or an output. When programmed as inputs, they can monitor external, TTL-compatible logic circuits. In the output mode, these pins are controlled by the I/O1 and I/O2 bits in the downstream C/I channel. In the output or input modes, the logic state of these pins appears in the I/O1 and I/O2 bits of the upstream C/I channel. When programmed as outputs, they can control an external logic device or they can be connected to pin C3, C4, or C5 of the ASLIC device to control test relay drivers RY1OUT, RY2OUT, and RY3OUT.
DCL
Input
DD DGND DU FS
Input Gnd Output Input
I1
Input
IAB
Input
IBAT
Input
IDC IDIF
Output Input
I/O1, I/O2
Input/Output
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AM79212/Am79C202 Data Sheet
Pin Names IREF
Type Input
Description Current Reference. An external resistor (RREF) connected between this pin and analog ground generates an accurate on-chip reference current. This current is used by the ASLAC device in its DC Feed and loop-supervision circuits. Ring-Trip Sense. These pins are current summing nodes referenced to VREF. They provide terminations for external resistors RSR1 and RSR2 that sense the voltages on both sides of the ringing-feed resistor connected to the ring bus. To determine the ringing current in the loop, the ASLAC device finds the difference between the currents in these pins. Metallic Sense. ISUM is a current input pin and is fed by the ISUM pin of the ASLIC device. The current in this pin is used by the ASLAC device for supervisory and diagnostic functions. Control Port. This output port is TTL compatible and is controlled by the O1 bit (bit 2) in the downstream C/I channel. It can control an external logic device or it can be connected to pin C3, C4, or C5 of the ASLIC device to control relays. Reset. A logic 1 on this pin resets the ASLAC device to initial default conditions. A signal less than 100 ns in duration should not cause a reset. To ensure proper reset, the minimum length of a reset pulse is 50 s. GCI Channel Identification Straps. When the input pins are individually strapped to VCC or DGND, the ASLAC device can be coded to communicate with one of the eight GCI channels within a frame. Analog Power Supply. VCCA is internally connected to substrate near the analog I/O section. Digital Power Supply. VCCD is internally connected to substrate near the digital section. Analog Input. The analog output (VTX) from the ASLIC device is applied to the ASLAC device transmit path input, VIN. The signal is sampled, processed, encoded, and placed on the upstream GCI port. Inversion of Analog Input. An inverted version of the analog input voltage on VIN appears on this pin. Longitudinal Reference. VLBIAS is programmed by VOFF and supplies the longitudinal reference voltage for the longitudinal control loop to the ASLIC device. 12 kHz or 16 kHz Metering Signal. For 12 kHz or 16 kHz teletax, an internally generated and shaped 12 kHz or 16 kHz sine wave metering pulse is output from this pin. Analog Output. The voice data from the downstream GCI port, B1 channel, is digitally processed and converted to an analog signal that is sent out of the VOUT pin to the ASLIC device. Analog Reference. This pin provides a voltage reference to be used as the analog zerolevel reference on the ASLIC device.
IRTA, IRTB
Inputs
ISUM
Input
O1
Output
RST
Input
S0, S1, S2
Input
VCCA VCCD VIN
Power Power Input
VINM VLBIAS VM VOUT
Output Output Output Output
VREF
Output
ASLIC/ASLAC Products
9
ASLIC/ASLAC DEVICES FUNCTIONAL DESCRIPTION
The ASLIC/ASLAC devices chip set integrates all functions of the subscriber line. The chip set comprises an ASLIC device and an ASLAC device. The set provides two basic functions: 1) the ASLIC device, a high-voltage, bipolar device that drives the subscriber line, maintains longitudinal balance, and senses line conditions, and 2) the ASLAC device, a low-voltage, CMOS device that combines CODEC, DC Feed control, and line supervision. A complete schematic of a linecard using the ASLIC/ASLAC devices chip set is shown in Figure 7. The ASLIC device uses reliable, bipolar technology to provide the power necessary to drive a wide variety of subscriber lines. It can be programmed by the ASLAC device to operate in eight different states that control Power Consumption and Signaling modes. This enables full control over the subscriber loop. The ASLIC device is customized to be used exclusively with the ASLAC device providing a two-chip universal line interface. The ASLIC device requires only a +5 V power supply and a negative battery supply for its operation. The ASLIC device implements a linear loop current feeding method with the enhancement of thermal management to limit the amount of power dissipated on the ASLIC device by dissipating excess power in an external resistor. The ASLAC device is a high-performance, CMOS CODEC/filter device with additional digital filters and circuits that allow software control of transmission, DC Feed, and supervision. Advanced CMOS technology makes the ASLAC device an economical device that has both the functionality and the low power consumption required by linecard designers to maximize linecard density at minimum cost. When used with an ASLIC device, the ASLAC device provides a complete software-configurable solution to linecard functions as well as complete programmable control over subscriber line DC Feed characteristics. In addition, the ASLIC/ASLAC devices chip set provides system-level solutions for the loop supervisory functions and metering. In total, the ASLIC/ASLAC devices chip set provides a programmable solution that can satisfy worldwide linecard requirements by software configuration. All software-programmed coefficients and DC Feed parameters are easily calculated with the AmSLAC3(c) software. This software is provided free of charge and runs on an IBM-compatible PC. It allows the designer to enter a description of system requirements, then the software returns the necessary coefficients and the predicted system response. The ASLAC device uses the General Control Interface (GCI) protocol to interface with the back plane highway. The ASLIC device interface unit inside the ASLAC device processes information regarding line voltages, loop currents, and battery voltage levels. These inputs allow the ASLAC device to place several key ASLIC device performance parameters under programmable supervision. The main functions that can be observed and/or controlled through the ASLAC device control interface are: DC Feed characteristics Ground-key detection Off-hook detection Metering signal Longitudinal operating point Subscriber line voltage and currents Ring trip Abrupt and smooth battery polarity reversal
To accomplish these functions, the ASLAC device collects the following information from the ASLIC device and the Central Office system: The sum and difference of the currents in each loop leg, ISUM, and IDIF Currents proportional to: -- The voltage across the loop (IAB) -- The battery voltage (IBAT) -- The ringing current in the loop (IRTA - IRTB)
The ASLAC device performs the CODEC and filter functions associated with the four-wire section of the subscriber line circuitry in a digital switch. These functions involve converting an analog voice signal into digital PCM samples and converting digital PCM samples back into an analog signal. During conversion, digital filters are used to band-limit the voice signals. The user-programmable filters set the receive and transmit gain, perform the transhybrid balancing function, permit adjustment of the two-wire termination impedance, and provide frequency attenuation adjustment (equalization) of the receive and transmit paths. Adaptive transhybrid balancing is also included.
10
AM79212/Am79C202 Data Sheet

The outputs supplied by the ASLAC device are then: A current proportional to the desired DC loop current (IDC) A voltage proportional to the desired longitudinal offset voltage (VLBIAS) A 12/16 kHz metering signal (appears on VM for 12/16 kHz teletax)
The PCM data can be either 8-bit companded A-law or -law code. Voice and control data are read or written to the digital interface in channels that are pin strap compatible. Besides the CODEC functions, the ASLAC device provides all the sensing, feedback, and clocking necessary to completely control ASLIC device functions with programmable parameters. System-level parameters under programmable control include active and disable loop-current limits, feed resistance, and apparent battery-feed voltage. The longitudinal operating point is programmable to optimize the ASLIC device signal swing capability.
The ASLAC device provides signals at 12 or 16 kHz for metering functions. The frequency and level of these signals are programmable. The ASLAC device provides extensive loop supervision capability, including off-hook, ring-trip, and ground-key detection. Detection thresholds for these functions are programmable. A programmable debounce timer is available that eliminates false detection due to contact bounce. For subscriber line diagnostics, AC and DC line conditions can be monitored using special test modes. Results are sent upstream over the control interface.
ASLIC/ASLAC Products
11
ELECTRICAL REQUIREMENTS Power Dissipation
Loop resistance = 0 to (not including fuse resistors), 2 x 50 fuse resistors, VBAT = -48 V, VCC = +5 V. For power dissipation measurements, DC Feed conditions are programmed as follows: VAPP (Apparent voltage) = 50.2 V ILA (Active state current limit) = 42.3 mA ILD (Disable state current limit) = 21.2 mA RFD (Feed resistance) = 807 VAS (Anti-sat activate voltage) = 8.2 V N2 (Anti-sat feed resistance factor) = 2 VOFF (Longitudinal offset voltage) = 6 V RTMG (Thermal management resistor) = 1200 RREF (Referenced current setting resistor) = 7.87 k Table 1. Power Dissipation
Description Test Conditions On-hook Disconnect ASLIC device power dissipation Normal polarity On-hook Standby On-hook Disable On-hook Active Off-hook Active RL = 294 Off-hook Disable RL = 600 ASLAC device power dissipation MCLK, PCLK = 2.048 MHz ASLAC device Activated ASLAC device Inactive, C/I Standby state command issued Min Typ 30 50 120 330 850 800 85 22 Max 70 105 215 450 1200 950 110 25 mW Unit
Thermal Resistance The junction-to-air thermal resistance of the ASLIC device in a 32-pin, PLCC package will be less than 45C/ W. The junction-to-air thermal resistance of the ASLAC device in a 32-pin, PLCC package will be less than 45C/ W.
12
AM79212/Am79C202 Data Sheet
ABSOLUTE MAXIMUM ELECTRICAL AND THERMAL RATINGS ASLIC Device
Storage temperature .................. -55C TA +150C Ambient temperature, under Bias............................... -40C TA +85C Ambient relative humidity (noncondensing) ..................................... 5 to 100% VCC with respect to AGND/DGND ........ -0.4 V to +7 V VBAT with respect to BGND ................ +0.4 V to -75 V VCC with respect to VBAT ....................................+80 V BGND with respect to AGND/DGND ................................ -0.5 V to +0.5 V Voltage on relay outputs .......................................+7 V AD or BD to BGND: Continuous..................................... -75 V to +1.0 V 10 ms (f = 0.1 Hz) ............................. -75 V to +5 V 1 s (f = 0.1 Hz) .............................. -90 V to +10 V 250 ns (f = 0.1 Hz) ........................ -120 V to +15 V Current into SA or SB: 10 s rise to Ipeak; 1000 s fall to 0.5 Ipeak; 2000 s fall to I = 0 ..........................Ipeak = 5 mA Current into SA or SB: 2 s rise to Ipeak; 10 s fall to 0.5 Ipeak; 20 s fall to I = 0 .........................Ipeak = 12.5 mA Current through AD or BD..............................150 mA C5-C1 to DGND or AGND................-0.4 V to VCC + 0.4 V Maximum power dissipation, TA = 70C ...........1.67 W
Note: Thermal limiting circuitry on chip will shut down the circuit at a junction temperature of about 160C. The device should never be exposed to this temperature. Operation above 145C junction temperature may degrade device reliability. See the SLIC Packaging Considerations for more information.
ASLAC Device
Storage temperature...................-60C TA +125C Ambient temperature, under Bias ...............................-40C TA +85C Ambient relative humidity (noncondensing)......................................5 to 100% VCCA, VCCD with respect to DGND....... -0.4 V to + 6 V VCCA with respect to VCCD ................................ 0.4 V VIN with respect to DGND ....... -0.4 V to VCCA + 0.4 V AGND .....................................................DGND 0.4 V Latch up immunity (any pin) .......................... 100 mA Any other pin with respect to DGND ................. -0.4 V to VCC + 0.4 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability.
OPERATING RANGES Environmental
Ambient temperature ......... 0C to +70C Commercial* Ambient relative humidity ......................... 15% to 85% ASLIC Device VCC .............................................................. +5 V 5% VBAT ..................................................... -18 V to -70 V BGND with respect to GND ........ -100 mV to +100 mV Load resistance on VTX to ground............... 10 k min ASLAC Device Supplies VCCA, VCCD................................ +5.0 V 5% DGND ..................................................................... 0 V AGND ..................................................DGND 50 mV
Operating ranges define those limits over which the functionality of the device is guaranteed by production testing. * Functionality of the device from 0C to +70C is guaranteed by production testing. Performance from -40C to +85C is guaranteed by characterization and periodic sampling of production units.
ASLIC/ASLAC Products
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PERFORMANCE CHARACTERISTICS (See Note 1)
(See note 1) TA = 0C to 70C unless otherwise noted. Table 2. ASLIC Device DC Specifications
No. 1 Item 2-wire loop voltage Condition Standby state, RL = 1 Meg Active state, RLAD-BD = 600 IRSN = 140 A Disable state, RLAD-BD = 600 IRSN = 80 A 2 3 Feed resistance per leg at pins AD and BD ISUM current IDIF current Standby state Standby state, RL = 1930 Standby state A to VBAT B to ground Min VBAT - 1.8 19.51 11.34 130 44.6 35.4 43.4 Typ VBAT - 1.1 21.1 12.19 250 56 A Max VBAT - 0.5 22.68 V 13.04 375 Unit Note 4
4
Ternary input voltage boundaries for C2-C1 pins. Midlevel input source must be high impedance or 3-state Low boundary High boundary Logic inputs C2-C1 Input High current Input Low current 3-state voltage IC1 = IC2 = 1 A 0.8 2.0 0.8 -200 -400 BAL1 pin open IREF = 1 mA Tj < 145C, VDC is referenced to VREF, 35.7 k resistor connected from VDC to VREF. VSA - VSB = 40 V. IVDC = 20 A 4.2 5.58 20 VLBIAS = 3 V ILOOP = 10 mA ILONG = 10 mA 1/333 1/667 1/300 1/600 1/273 1/546 VCC - 0.4 6.0 33.3 6.42 V V/V k 4 -50 2.0 2.1 40 A Input Low current 40 +50 2.2 mV V VCC - 1 -80 90 200 A 200 3.5 V 4 0.8 V
5
Logic inputs C5-C3 Input High voltage Input Low voltage Input High current
6 7 8
VTX output offset VREF input voltage , Ratio of VDC to loop voltage: VDC - VREF = -----------------------------------VSA - VSB Thermal shutdown threshold voltage output on VDC Gain from VLBIAS pin to AD or BD pin Input resistance to AGND, VLBIAS pin ISUM/ILOOP IDIF/ILONG
0.0253
0.0242
0.0232
V/V
9
10 11 12 13
14
AM79212/Am79C202 Data Sheet
Table 2. ASLIC Device DC Specifications (continued)
No. 14 15 16 17 18 Item Input current, SA and SB pins Input current HPA and HPB pins IDC input impedance K1 Metallic offset current Incremental DC Current Gain 1.26 Condition Min Typ 1 0.1 1.8 254 0 -0.4 Max 3 A 3 3 k A/A 13 mA 4 Unit Note
ASLIC Device Relay Driver Schematic
RINGOUT RY1OUT RY2OUT RY3OUT
BGND
Table 3. ASLIC Device Relay Driver Specifications
Item Condition 25 mA per relay sink On voltage 40 mA per relay sink 1 relay on 4 relays on Off leakage, each relay driver. VOH = +6 V 0 0.45 0.8 0.7 +1.0 100 A 4 1 relay on 4 relays on Min Typ 0.225 0.4 Max +0.3 0.5 V 4 Unit Note
Table 4. ASLIC Device Transmission Specifications
No. 1 2 3 4 5 6 7 8 Item RSN input impedance VTX output impedance Gain, BAL1 to VTX Gain, BAL2 to VTX BAL1 input impedance BAL2 input impedance Input impedance A or B to GND 2- to 4-wire gain TA = 0C to70C, -10 dBm, 1 kHz TA = -40C to 0C/70C to 85C -12.19 -12.24 1.4 2.8 3.17 2.09 Condition f = 300 Hz to 3400 Hz Min Typ 1 3 1.5 3.0 5 3.3 70 -12.04 1.6 V/V 3.2 7.5 k 4.95 135 -11.89 -11.84 dB 4 Max Unit Note
ASLIC/ASLAC Products
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Table 4. ASLIC Device Transmission Specifications (continued)
No. 9 10 Item 2- to 4-wire gain variation with frequency 2- to 4-wire gain tracking Condition 300 to 3400 Hz relative to 1 kHz TA = -40C to 0C/70C to 85C +3 dBm to -55 dBm Reference: -10 dBm TA = -40C to 0C/70C to 85C -10 dBm, 1 kHz TA = -40C to 0C/70C to 85C 300 to 3400 Hz relative to 1 kHz TA = -40C to 0C/70C to 85C +3 dBm to -55 dBm Reference: -10 dBm TA = -40C to 0C/70C to 85C 300 Hz to 3400 Hz 0 dBm +4 dBm -12 dBm -8 dBm VLBIAS = 2.4 V, ILOOP = 30 mA, VBAT = -60 V, DC Load = 200 , Load at 16 kHz = 10 k Active and Disable states 2-wire TA = -40C to 0C/70C to 85C 4-wire 2-wire TA = -40C to 0C/70C to 85C 4-wire L-T 200 to 1000 Hz TA = -40C to 0C/70C to 85C 1000 to 3400 Hz TA = -40C to 0C/70C to 85C T-L 200 to 3400 Hz 58 53 53 48 40 63 50 48 25 25 45 40 dB 3, 5 4 4, 8 2 12 25 25 45 35 3, 5 2, 4 4 42 Min -0.1 -0.15 -0.1 -0.15 -0.15 -0.20 -0.1 -0.15 -0.1 -0.15 0 Typ Max +0.1 +0.15 +0.1 +0.15 +0.15 +0.20 +0.1 +0.15 +0.1 +0.15 -50 -40 -50 -40 Vp-p 4 dB Unit Note
11 12 13
4- to 2-wire gain 4- to 2-wire gain variation with frequency 4- to 2-wire gain tracking
14
Total Harmonic Distortion 2-wire 4-wire 2-wire metering overload level
15
Idle channel noise C-message weighted Psophometric weighted
+7 -5 -83 -95 63 58
+11 +15
dBrnC 4 4
-79 -75
dBmp 4
16
Longitudinal balance (IEEE method) Normal Polarity
L - T, IL = 0 50 to 3400 Hz Reverse Polarity 17 PSRR (VBAT) L-T 200 to 1000 Hz TA = -40C to 0C/70C to 85C 50 to 3400 Hz 3.4 kHz to 50 kHz ASLIC device in Anti-Sat state (Loop open) f = 50 Hz, CB = 100 nF f = 200 to 3400 Hz, CB = 100 nF 18 PSRR (VCC) 50 to 3400 Hz 3.4 kHz to 50 kHz
16
AM79212/Am79C202 Data Sheet
Table 4. ASLIC Device Transmission Specifications (continued)
No. 19 20 Item Low frequency induction (REA method) Longitudinal AC current per wire Condition Active state, VLONG = 30 V rms, IL = 20 mA, f = 60 Hz f = 15 to 60 Hz 20 Min Typ Max +23 Unit dBrnC 4 mArms Note
Table 5. ASLAC Device DC Specifications
No. 1 Item Input Low voltage DD, FS, DCL, RST, I1, I/O1, I/O2 S0, S1, S2 2 Input High voltage DD, FS, DCL, RST, I1, I/O1, I/O2 S0, S1, S2 3 Input leakage current DD, FS, DCL, RST, I1, I/O1, I/O2, S0, S1, S2 Input hysteresis DD, FS, DCL, RST Ternary output voltages C2-C1 High voltage Low voltage Output current 6 Output Low voltage on digital outputs I/O1, I/O2, 01, DU Output High voltage I/O1, I/O2, 01 IOUT = 200 A IOUT = 200 A Mid level IOL = 10 mA IOL = 2 mA -1 VCC - 0.85 0.65 +1 1.0 0.4 V A V Condition Min -0.4 Typ Max 0.8 Unit Note
-0.4 2.0
0.6 V VCC + 0.5
VCC - 0.5 -10
VCC + 0.4 +10 A
4
0.5
V
4
5
7
IOH = 400 A
VCC - 0.4
ASLIC/ASLAC Products
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Table 5. ASLAC Device DC Specifications (continued)
No. 8 DC Feed Item Condition ILA = 47.6 mA, RFD = 403 , N2 = 2, VAS = 10.3 V, IBAT = 69.9 A Active state, Normal polarity, IAB = 0, VAPP = 50.2 V Min Typ Max Unit Note 17
IDC
172.7
188.5
204.9
A
IAB -------------IDC IAB
In resistive-feed region
0.0624
0.0694
0.0764
A/A
IBAT = 69.9 A Adjust IAB until IDC = 0 Programmed VAPP = 50.2 V Programmed VAS = 10.3 V Any ILA or ILD programmed value > 20 mA (IDC > 78.7 A) Any ILA or ILD programmed value 20 mA (IDC 78.7 A)
27.93
29.93
31.93
A
17
Measured VAPP Measured VAS 9 IDC error among programmed ILA, ILD
2.2 V 1.6 5 % A +50 mV 4, 17
4
17
10
Offset voltage allowed on VIN VOUT offset voltage AISN off AISN on
-50
10
11
-40 -80 2.0 2.1
+40 mV +80 2.2 V 17 10, 17
12
Output voltage, VREF Capacitance load on VREF or VOUT Output current VOUT Input resistance IDIF pin to VREF VLBIAS operating voltage Percent error of VLBIAS voltage Capacitance load on VLBIAS Capacitance load on IRTA or IRTB
Load current = 0 to 1 mA Source or sink
13
200
pF 4
14 15
Source or sink
-1 8.84 13.6
+1 18.36
mA k 6
16
Source current < 250 A or sink current < 25 A For VLBIAS equation, see Longitudinal Control Loop section
+1
+2.4
V 17
17
-5
+5
%
18
120 pF 6
19
400
18
AM79212/Am79C202 Data Sheet
Table 6. ASLAC Device Transmission and Signaling Specifications
No. 1 Item Insertion loss Condition Input: 1014 Hz, -10 dBm0 RG = AR = AX = GR = GX = 0 dB, AISN, R, X, B, and Z filters disabled TA = 0C to 70C TA = -40C to 0C/70C to 85C TA = 0C to 70C TA = -40C to 0C/70C to 85C TA = 70C TA = 0C to 70C; VCC = 4.75 - 5.25 V TA = -40C to 0C/70C to 85C A-D AX + GX Min Typ Max Unit Note
A-D D-A A-D + D-A
-0.25 -0.30 -0.25 -0.30 -0.20 -0.25 -0.34 -0.1
0 0 0 0
+0.25 +0.30 +0.25 +0.30 +0.20 +0.25 +0.34 dB +0.1
7
2
Level set error (Error between setting and actual value)
D-A 3 DD to DU gain in Full Digital Loopback mode
AR + GR
-0.1
+0.1
DD Input: 1014 Hz, -10 dBm0 RG = AR = AX = GR = GX = 0 dB, AISN, R, X, B, and Z filters disabled TA = 0C to 70C TA = -40C to 0C/70C to 85C AX = 0 dB AR = 0 dB
-0.2 -0.25
+0.1
+0.4 +0.50
4
Idle channel noise, psophometric weighted (A-law)
dBm0p A-D (PCM output) D-A (VOUT) 5 Idle channel noise, C-message weighted (-law) AX = 0 dB AR = 0 dB dBrnC0 A-D (PCM output), GX = +8 dB D-A (2 wire), GR = -8 dB 6 7 8 9 Coder offset decision value, Xn GX step size GR step size PSRR (VCC) image frequency A-D, Input signal = 0 V, A-law 0 GX < 10 dB 10 GX 12 dB -12 GR 0 dB Input: 4800 to 7800 Hz 200 mV p-p Measure 8000 Hz input frequency A-D D-A 10 Group delay PCLK 1.53 MHz PCLK 1.03 MHz 1014 Hz; -10 dBm0 B, X, R, and Z filters programmed with null coefficients 37 dB 37 590 655 s -5 +16 +12 +5 0.1 0.3 0.1 Bits -68 -78
12
6
dB
4
4
4, 14
ASLIC/ASLAC Products
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Table 6. ASLAC Device Transmission and Signaling Specifications (continued)
No. 11 Item Switchhook thresholds Switchhook hysteresis 12 Ground-key thresholds Ground-key hysteresis 13 14 Voltage that sets thermal shutdown bit IDIF fault current thresholds FT, pkFT FT, pkFT hysteresis 15 AISN gain accuracy GAISN = 0.0625 GAISN = 0.125 GAISN = 0.1875 GAISN = -0.25 or GAISN +0.25 16 17 18 19 20 Metering voltage (MTRA) accuracy Metering voltage noise Ring-trip accuracy Ring-trip hysteresis Power-cross accuracy Measured at ASLAC device VM pin Wide-band signal to noise 0C to 70C VZX IZX During transmission During ringing -10 -10 -16 -8 -6 -4 -7 40 -5 4 5 +10 +10 % +5 Voltage on ASLIC device VDC with RAB = 35.7 k Tip-to-battery fault current (mA) 19.3, 50.6 -10 -10 +16 +8 +6 +4 +7 dB % V A 4, 16, 19 -- 4, 16 19 4, 16, 19 % +10 9, 15, 18 4 +4.19 All TGK settings -0.90 or -10 -10 Condition All TSH settings Min -0.45 or -10 -10 +0.90 or +10 Typ Max +0.45 or +10 Unit mA % % mA % % 4 V 9, 15, 18 9, 15, 18 4 Note
Notes: 1. Unless otherwise specified, test conditions are: VCC = 5 V, RTMG = 1200 , BAT = -51 V, RAB = 35.7 K, RBAT1 = RBAT2 = 365 k, RREF = 7.87 k, RRX = 75 k, RL = 600 , RSA = RSB = 200 k, CHP = 220 nF, CDC1 = 1.0 F, 50 fuse resistors, RSR1 = RSR2 = 750 k, CAD = CBD = 22 nF, CB = 100 nF and the following network is connected between VTX and RSN: RT1 18.75 K VTX CT 430 pF RT2 18.75 K RSN
20
AM79212/Am79C202 Data Sheet
Ambient temperature = 70C Active state, normal polarity for transmission performance 0 dBm = 1 mW @ 600 (0.775 V rms) Programmed DC Feed conditions: VAPP (Apparent battery voltage) = 50.2 V ILA (Active state loop-current limit) = 47.6 mA ILD (Disable state loop-current limit) = 21.2 mA RFD (DC Feed resistance) = 403 VAS (Anti-sat activate voltage) = 10.3 V N2 (Anti-sat feed resistance factor) = 2 VOFF (Longitudinal Offset Voltage) = 8.4 V RG = GX = GR = AX = AR = 0 dB R, X, B, and Z filter disabled AISN = 0 TSH < ILD TSH = Programmed switchhook-detect threshold current. ILD = Programmed disable limit current. DC Feed conditions are normally set by the ASLAC device. When the ASLIC device is tested by itself, its operating conditions must be simulated as if it were connected to an ideal ASLAC device. When the ASLAC device is tested by itself, its operating conditions must simulate as if it were connected to an ideal ASLIC device. 2. These tests are performed with the following load impedances: Frequency < 12 kHz - Longitudinal impedance = 500 ; metallic impedance = 300 Frequency > 12 kHz - Longitudinal impedance = 90 ; metallic impedance = 135 3. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization. 4. Not tested or partially tested in production. This parameter is guaranteed by characterization or correlation to other tests. 5. When the ASLIC device is in the anti-sat operating region, this parameter will be degraded. The exact degradation will depend on system design. 6. Guaranteed by design. 7. Overall 1.014 kHz insertion loss error of the ASLIC/ASLAC devices kit is guaranteed to be 0.34 dB. 8. The VBAT PSRR specifications are valid only when the ASLIC device is used with the ASLAC device which generates the anti-sat reference. Because the anti-sat reference depends upon the battery voltage sensed by the IBAT pin of the ASLAC device, the PSRR of the kit will depend upon the amount of battery filtering provided by CB. 9. Must meet at least one of these specifications. 10. These voltages are referred to VREF. 11. These limits refer to the two-wire output of an ideal ASLIC device but reflect only the capabilities of the ASLAC device. 12. When relative levels (dBm0) are used, the specification holds for any setting of (AX + GX) gain from 0 to 12 dB or (AR + GR + RG) from 0 to -12 dB. 13. This parameter tested by inclusion in another test. 14. The Group Delay specification is defined as the sum of the minimum values of the group delays for the transmit and the receive paths when the transmit and receive time slots are identical and the B, X, R, Z filters are disabled with null coefficients. For PCLK frequencies between 1.03 MHz and 1.53 MHz, the group delay may vary from one cycle to the next. See Figure 2, Group Delay Distortion also. 15. These limits reflect only the capabilities of the ASLAC device. 16. RSR1 = RSR2 = 750 k, 0% tol. RGFD1 = 510 . 17. DC Feed performance derates by 5% when operating from -40C to 0C and 70C to 85C. 18. Threshold values derate by 5% when operating from -40C to 0C and 70C to 85C. 19. Power cross and ring trip values derate by 5% when operating from -40C to 0C and 70C to 85C.
ASLIC/ASLAC Products
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The transmit path is defined as the section between the analog input to the ASLAC device (VIN) and the GCI voice output of the ASLAC device A-law/-law speech compressor (see the Voice Transmission Path figure in the Technical Reference). The receive path is defined as the section between the GCI voice input to the ASLAC device speech expander and the analog output of the ASLAC device (VOUT). All limits defined in this section are tested with B = 0, Z = 0, and X = R = RG = 1. When RG is enabled, a nominal gain of -6.02 dB is added to the digital section of the receive path. When AR is enabled, a nominal gain of -6.02 dB is added to the analog section of the receive path. When AX is enabled, a nominal gain of +6.02 dB is added to the analog section of the transmit path. When the gains in the transmit path are set to AX = 0 dB and GX = 0 dB, a 1014 Hz sine wave with a nominal voltage of 0.596 V rms for -law and 0.6 V rms for A-law at the ASLAC device analog input will correspond to a level of 0 dBm0 at the GCI voice output. Under these conditions, the overload level of the transmit path is 1.25 V peak referenced to VREF. When the gains in the receive path are set to AR = GR = 0 dB, a 1014 Hz sine wave with a level of 0 dBm0 at the GCI voice input will correspond to a nominal voltage of 0.596 V rms for -law and 0.6 V rms for A-law at the analog output of the ASLAC device. Under these conditions, the maximum receive output level is 1.25 V peak referenced to VREF. When relative levels (dBm0) are used in any of the following transmission characteristics, the specification holds for any setting of (AX + GX) gain from 0 dB to 12 dB or (AR + GR + RG) from 0 to -12 dB. These transmission characteristics are valid for 0C to 70C and for VCC = +5 V 0.25 V.
22
AM79212/Am79C202 Data Sheet
Attenuation Distortion The deviations from nominal attenuation will stay within the limits shown in Figure 1. The reference frequency is 1014 Hz and the signal level is -10 dBm0. Minimum transmit attenuation at 60 Hz is 24 dB.
2
ASLAC Device Specification
1 0.6 Attenuation (dB)
0.80 0.65
0.2 0.125 0 -0.125 Receive path
0 200 300 600
Frequency (Hz)
3000 3200 3400
Figure 1. Transmit and Receive Path Attenuation vs. Frequency
ASLIC/ASLAC Products
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Group Delay Distortion For either transmission path, the group delay distortion is within the limits shown in Figure 2. The minimum value of the group delay is taken as the reference. The signal level should be -10 dBm0.
420
ASLAC Device Specification (Either Path)
Delay (s)
150
90
0
500 600
1000 Frequency (Hz)
2600 2800
Figure 2. Group Delay Distortion Single Frequency Distortion The output signal level, at any single frequency in the range of 300 Hz to 3400 Hz, other than that due to an applied 0 dBm0 sine wave signal with frequency f0 in the same frequency range, is less than -46 dBm0. With f0 swept between 0 to 300 Hz and 3400 Hz to 12 kHz, any generated output signals other than f0 are less than -28 dBm0. This specification is valid for either transmission path. Intermodulation Distortion Two sine wave signals of different frequencies f1 and f2 (not harmonically related) in the range 300 Hz to 3400 Hz and of equal levels in the range -4 dBm0 to -21 dBm0 will not produce 2 * (f1 - f2) products having a level greater than -42 dB relative to the level of the two input signals. A sine wave signal in the frequency band 300 Hz to 3400 Hz with input level -9 dBm0 and a 50 Hz signal with input level -23 dBm0 will not produce intermodulation products exceeding a level of -56 dBm0. These specifications are valid for either transmission path.
24
AM79212/Am79C202 Data Sheet
Gain Linearity The gain deviation relative to the gain at -10 dBm0 is within the limits shown in Figure 3 (A-law) and Figure 4 (-law) for either transmission path when the input is a sine wave signal of 1014 Hz.
1.5
ASLAC Device Specification
0.55 0.25 Gain (dB) 0 -55 -50 -40 -10 0 +3 Input Level (dBm0)
-0.25 -0.55
-1.5 Note: Relax specification by 0.05 dB at -40C.
Figure 3. A-law Gain Linearity with Tone Input (Both Paths)
1.4
ASLAC Device Specification
0.45 0.25 Gain (dB) 0 -55 -50 -37 -10 0 +3 Input Level (dBm0)
-0.25 -0.45
-1.4
Note: Relax specification by 0.05 dB at -40C.
Figure 4. -law Gain Linearity with Tone Input (Both Paths)
ASLIC/ASLAC Products
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Total Distortion Including Quantizing Distortion The signal-to-total distortion ratio will exceed the limits shown in Figure 5 for either path when the input signal is a sine wave signal of frequency 1014 Hz. Improved distortion at lower levels in LSSGR applications can be obtained by proper selection of the GX and GR ranges.
ASLAC Device Specification B C D Signal-to-Total Distortion (dB) A A B C D
A-law 35.5 dB 35.5 dB 30 dB 25 dB
-Law 35.5 dB 35.5 dB 31 dB 27 dB
-45
-40
-30 Input Level (dBm0)
0
Figure 5. Total Distortion with Tone Input (Both Paths)
26
AM79212/Am79C202 Data Sheet
Overload Compression Figure 6 shows the acceptable region of operation for input signal levels above the reference input power (0 dBm0). The conditions for this figure are: (1) 1 dB < transmit path +12 dB; (2) -12 dB receive path < -1 dB; (3) Digital voice output connected to digital voice input; and (4) measurement analog-to-analog.
Fundamental Output Power (dBm0) 9 8 7 6 5 4 3 2.6 2 1 Acceptable Region
1
2
3
4
5
6
7
8
9
Fundamental Input Power (dBm0)
Figure 6. A/A Overload Compression
ASLIC/ASLAC Products
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SWITCHING CHARACTERISTICS Microprocessor Interface
Min. and Max. values are valid for all digital outputs with a 100 pF load, except DU which is valid with 8 loads, (see note 2). Table 7. Microprocessor Interface
No. 1 2 3 4 5 6 7 8 9 10 Symbol tFSW tFSR tFSF tFSS tFSH tDDC tDDF tIDS tIDH tRST Parameter FS High pulse width FS rise time of clock FS fall time of clock FS setup time FS hold time Output delay from DCL Output delay from FS Input data setup time Input data hold time Reset pulse width tDCH+20 50 50 70 50 100 150 Min. 130 60 60 tDCL-50 Typ. Max. Units ns ns ns ns ns ns ns ns ns s Note
Data Clock For 2.048 MHz 100 ppm or 4.096 MHz 100 ppm Table 8. Data Clock
No. 11 Symbol tDCY Parameter Data clock period (2.048 MHz) Data clock period (4.096 MHz) 12 13 14 15 tDCR tDCF tDCH tDCL Rise time of clock Fall time of clock DCL High pulse width DCL Low pulse width 90 90 Min. 478 239 Typ. 488.28 244.14 Max. 498 249 60 60 Units ns ns ns ns ns ns 1 1 Note 2
Notes: 1. The Data Clock (DCL) may be stopped in the High or Low state indefinitely without loss of information. 2. The drive capability of the GCI interface allows eight ASLAC devices per linecard (eight subscriber lines) without using external buffers.
28
AM79212/Am79C202 Data Sheet
SWITCHING WAVEFORMS Input and Output Waveforms for AC Tests
2.4 2.0 0.8
}
Test Points
{
2.0 0.8
0.45
Data Clock Timing - DCL
11 15 VIH VIL 14 12
13
ASLIC/ASLAC Products
29
GCI Waveforms
DCL
FS
DD, DU
Bit 7 Detail A
Bit 6
GCI Timing (Detail A) 12 13
DCL* 14 11 15
FS
4
5
1 7 DU 6 8 DD 9
* Timing diagram valid for fDCL = 4096 kHz
30
AM79212/Am79C202 Data Sheet
Table 9. User-Programmable Components
Z T = 63.5 * ( Z2WIN - 2R F ) ZT is connected between the VTX and RSN pins. The fuse resistors are RF. Z2WIN is the desired 2-wire AC input impedance. When computing ZT, the internal current amplifier pole and any external stray capacitance between VTX and RSN must be taken into account. ZRX is connected from VRX to RSN. ZT is defined above, and G42L is the desired receive gain.
ZL 254 * Z T Z RX = ----------- * -------------------------------------------------------G 42L Z T + 63.5 * ( Z L + 2R F )
Thermal Management Equations (Normal Active and Tip Open States) V BAT - VOFF R TMG = -----------------------------------I LOOP ( V BAT - VOFF - ( I LOOP * RL ) ) P RTMG = ---------------------------------------------------------------------------------R TMG
2
RTMG is connected from TMG to VBAT and is used to reduce power dissipation within the ASLIC device in normal Active and Tip Open states. Power dissipated in the thermal management resistor, RTMG, during normal Active and Tip Open states
2
P SLIC = VBAT * I LOOP - P RTMG - R L * ( ILOOP ) + 0.12 W
Power dissipated in the ASLIC device while in normal Active and Tip Open states
Thermal Management equations (Polarity Reverse State) Note: ASLIC device die temperature should not exceed 140C. P SLIC = VBAT * I LOOP - ( R L * ( I LOOP ) ) + 0.12 W T SLIC = P SLIC * jA + T AMBIENT ThetajA ( jA ) = 43C watt
2
Power dissipated in the ASLIC device while in the polarity reverse state Total die temperature Thermal impedance of the 32-pin plastic leaded chip carrier package
ASLIC/ASLAC Products
31
ASLIC/ASLAC DEVICES LINECARD
+5 V
ASLIC Device (32-Pin PLCC)
VCC GND VREF RSA SA RFA A K2A VCC K1A CAD AD IDC RSN
ASLAC device (32-Pin PLCC)
+5 V
+5 V
VCCA VCCD AGND VREF CDC1 IDC VOUT RRX DGND GCI BACK PLANE DD DU DCL FS RST S0 S1 S2 ID STRAPS IREF RREF
U2 U1
BAL2 NC CM BAL1 NC RM RT VM VTX VIN ISUM RAB IDIF IAB VLBIAS CDIF C5 VREF I1 O1 I/O2 I/O1 C2 C1 NC IBAT VBAT TMG RTMG CBAT RBAT2 RBAT1 CB + ISUM NC VINM
+
K1 K2 K3 K4 R T TEST E BUS S T C.O. BATTERY CS 3 1 U3 4 2
RINGOUT RY1OUT RY2OUT RY3OUT
+
CHP RSB
HPA HPB SB
IDIF VDC VLBIAS
K2B B K1B
RFB BD CBD
C4 C3 C2 C1 RSVD
+
BGND
RGFD1 RSR1
+
(-)
D1 C.O. BATTERY
IRTA
IRTB
RING BUS
RSR2
*These pins are unavailable for 32-pin PLCC option. Battery Ground Analog Ground Digital Ground
+
Polarized Capacitor
+
Non-polarized Capacitor + indicates bias
Figure 7. ASLIC/ASLAC Typical Linecard Schematic
32
AM79212/Am79C202 Data Sheet
Table 10. ASLIC/ASLAC Devices Linecard Parts List
Item U1 U2 U3 D1 RFA, RFB RSA, RSB RSR1, RSR2 Type ASLIC device ASLAC device LCP150S Diode Resistor Resistor Resistor 100 mA 50 200 k 750 k 2% 2% 2% 100 V 2W 1/4 W 1/4 W Transient Voltage Suppressor, SGS-Thomson 50 ns Fusible protection resistors Sense resistors Matched to within 0.2% for initial tolerance and 0C to 70C ambient temperature range.** 17 mW typ 1.2 W typ <1 mW 2.5 mW typ <1 mW <1 mW Application dependent <1 mW Used only if ringing tests are required Ceramic Ceramic, not voltage sensitive Ceramic, VBAT typ Ceramic, VBAT typ Ceramic, 0.5 Vbat typ Ceramic Ceramic Protector speed up capacitor DPDT Value Tol. Rating Comments
RGFD1 RRX, RT* RBAT1, RBAT2 RAB RREF RTMG * RM* RTEST CDIF CAD, CBD * CBAT CHP CB CDC1 CM* CS * K1, K2, K3, K4
Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Relay
510 16.9 k 365 k 35.7 k 7.87 k 1200 3.16 k 3 k 10 nF 22 nF 150 nF 220 nF 100 nF 1.0 F 1.8 nF 100 nF 5 V coil
2% 1% 1% 1% 1% 5% 1% 1% 20% 10% 20% 20% 20% 20% 10% 20%
2W 1/8 W 1/8 W 1/8 W 1/8 W 4W 1/8 W 5W 5V 100 V 100 V 100 V 100 V 5V 5V 100 V
Notes: * Value can be adjusted to suit application. ** Can be looser for relaxed ring trip requirements. 1% match (each resistor 0.5%) gives 1.275 mA uncertainty in ringing current sensing.
ASLIC/ASLAC Products
33
PHYSICAL DIMENSION
PL032
.447 .453 .485 .495 .009 .015 .125 .140 .080 .095 SEATING PLANE .400 REF. .013 .021 .026 .032 TOP VIEW .050 REF. .490 .530 .042 .056
.585 .595 .547 .553
Pin 1 I.D.
SIDE VIEW
16-038FPO-5 PL 032 DA79 6-28-94 ae
REVISION SUMMARY Revision A to Revision B
* * * * * Under Connection Diagrams, Top View, fixed the ASLIC device to read AM79212 instead of Am79C212. Minor changes were made to the data sheet style and format to conform to Legerity standards. The physical dimension (PL032) was added to the Physical Dimension section. Updated the Pin Description table to correct inconsistencies. Minor changes were made to the data sheet style and format to conform to Legerity standards.
Revision B to Revision C
34
AM79212/Am79C202 Data Sheet
The contents of this document are provided in connection with Legerity, Inc. products. Legerity makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in Legerity's Standard Terms and Conditions of Sale, Legerity assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. Legerity's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of Legerity's product could create a situation where personal injury, death, or severe property or environmental damage may occur. Legerity reserves the right to discontinue or make changes to its products at any time without notice.
(c) 1999 Legerity, Inc. All rights reserved.
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